1. Field of the Invention
The present invention relates to a multi-bank semiconductor memory device and a method for arranging input and output (I/O) lines. More particularly, the invention relates to an improved architecture leading to efficiency in chip manufacture and design.
2. Description of the Related Art
A semiconductor memory device may employ different architecture such as multi-bit architecture or multi-bank architecture to enhance performance. In multi-memory bank architecture, memory banks can be readily accessed independently and selectively by a bank address method.
In such a multi-memory bank architecture, a write operation, a read operation, and an interrupt operation can be performed in different memory banks. The multi-memory bank architecture includes a bank data bus, which may be a global I/O line, carrying the data read from each memory bank and the data to be written.
Further, each memory bank is divided into a plurality of memory blocks according to the increasing number of memory cells included in one memory bank. The plurality of memory blocks are connected to global I/O lines through a plurality of local I/O lines. Accordingly, each memory block should include sense amplifier blocks, word-line driving blocks, sense amplifier driving circuits, and line transfer circuits because each memory bank is divided into a plurality of memory blocks.
The above-described multi-memory bank architecture is disclosed in U.S. Pat. No. 5,781,495. Specifically, the disclosed architecture includes a plurality of global I/O line pairs passing through the upper side of a memory cell array and extended across a plurality of memory banks.
The efficiency of such multi-memory bank architecture suffers however due to the added size.
Therefore a need exists for a multi-memory bank architecture to improve cell efficiency and chip efficiency.